Field induced charge device model (CDM) damage from an electrostatic field occurs when a charged item it brought into close proximity to an electrostatic discharge (ESD) sensitive device and the device is then grounded while in the presence of the field. Effective ESD control programs ensure that process-required insulators will not induce damaging voltage levels onto the devices being handled.
CDM emulates an integrated circuit that becomes charged during handling and discharges to a grounded metallic surface. The capacitance is the capacitance of the integrated circuit to its surroundings and the discharge path is a pin of the IC directly to a grounded surface. The test method for CDM must have a capacitance that scales with the device under test's (DUT) capacitance and a discharge path with very little impedance other than the DUT's own pin impedance. The peak current for CDM ESD is larger than other ESD models, e.g., human body model (HBM).
Existing conventional ESD protection schemes for internal logic circuits degrade RF circuit performance. This occurs because the ESD-induced parasitic capacitance negatively impacts an input matching network in RF front-end circuits such as a low-noise amplifiers, especially for millimeter wave IC applications.
FIG. 1 portrays a prior art RFIC design 10 having a conventional ESD protection circuit (primary ESD protection) and secondary ESD protection for CDM. In the illustrated design 10, the ESD protection circuit includes a dual-diode rectifier circuit 14 with a power clamp 16 serving as primary ESD protection element for a RFIC, for example a low-noise amplifier (LNA) 12 as shown. More specifically, LNA 12 is configured as a source-degenerated CMOS cascode LNA. LNAs typically form the first stage of RF front-end circuits. With the double-diode configuration, one diode element is forward-biased and the other is reverse-biased during an ESD event, which can compensate for the voltage dependence of the diode parasitic capacitance and lessen the impact of the DC voltage swing. The power clamp is placed as close as possible to the RF input pins to reduce the interconnect resistance and the associated voltage drop. The secondary ESD protection is provided by a gate-grounded NMOS (GGNMOS) device 18 in close proximity to the NMOS (M1) of the LNA 12. This GGNMOS secondary ESD protection approach has its deficiencies. For example, the large induced parasitic capacitance from the GGNMOS device 18 negatively impacts the RF performance, such as the noise figure. Moreover, the presence of the GGNMOS significantly impacts the impedance match along the signal path of the RF circuit.
The RF circuit of FIG. 1 also includes a capacitor 20 coupled between the gate and source of the NMOS transistor M1. The capacitor is provided for noise optimization under power-constrained simultaneous noise and input matching (PCINM). This design balances the contribution of the transistor noise and the noise due to the parasitic gate-circuit resistances. The extra gate-source capacitor gives an additional degree of freedom while taking the integrated inductor losses into account. Details of the use of this capacitor are provided in Belostotski, “Noise Figure Optimization of Inductively Degenerated CMOS LNAs with Integrated Gate Inductors”, IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol. 53, No. 7 (July 2006), the entirety of which is hereby incorporated by reference herein.
FIG. 2 shows a prior art multi-stage RF circuit 50. Specifically, the RF circuit has cascaded amplifier stages 12 and 12′. Directly adding conventional CDM ESD protection in the form of the GGNMOS 18′ impacts the input matching network and the inter-stage matching network, which significantly affects the RF performance.